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19-0860; Rev 0; 10/07
HDMI 2:1 Low-Frequency Translating Switch
General Description
The MAX4929E low-frequency 2:1 switch is ideal for HDMITM/DVITM switching applications. The device features a voltage clamp function to protect low-voltage systems at the output. The MAX4929E operates with a single 5V supply or dual or triple supplies. The MAX4929E provides clamping and voltage translation without additional components. All external inputs/outputs are electrostatic-discharge (ESD)-protected to 6kV Human Body Model (HBM). The MAX4929E is available in 20-pin QSOP and 20-pin, 4mm x 4mm, TQFN packages. The device is specified for the extended -40C to +85C operating temperature range. o DDC Switches Low 20pF (typ) Capacitance o Protects EDID (Extended Display Identification Data) EPROM or MCU from Excess Voltage o Hot-Plug Detect Signal Translates MCU Voltage to TTL Levels o Two Devices Can Be Used to Form a 4:1 Switch No Added Active Components Needed o 6kV ESD Protection HBM on All External I/Os o Available in Lead-Free, 20-Pin TQFN or 20-Pin QSOP Packages
Features
MAX4929E
Applications
HD Television Receivers HD Monitors High-Resolution Computer Monitors
Ordering Information
PART TEMP RANGE PINPACKAGE 20 QSOP 20 TQFN-EP* PKG CODE E20-1 T2044-3
MAX4929EEEP+ -40C to +85C
HDMI is a trademark of HDMI Licensing, LLC. DVI is a trademark of Digital Display Working Group (DDWG).
MAX4929EETP+ -40C to +85C
+Denotes a lead-free package *EP = Exposed paddle.
Typical Operating Circuit
+5V +3.3V TO +5V
Pin Configurations
SDAO
12
HIZ2
HDMI1 TMDS1
V+
CLP 2k 2k VDD SCLO SDAO EXESD 0.1F
EXESD 18 HPDO2 19
15 HIZ1 16 GND 17
14
HPD
0.1F
13
HPIR1 SCL1 SDA1 HPDO1 TMDS1
SCLO
11 10 9 SEL VL CLP V+ SCL1
0.1F
TOP VIEW
EDID EPROM
HPIRO
MAX4929E
*EP
8 7 6
MAX4929E
HPIR2 SCL2 SDA2 HPDO2 HIZ2 HIZ1
HPIR2 20 1 2 3 4 5
HDMI2
HPIR1
SCL2
+2V to +3.3V SEL HPIRO HPD VDD MCU 0.1F
TQFN (4mm x 4mm)
*EXPOSED PADDLE CONNECTED TO GND OR LEAVE EP UNCONNECTED
Pin Configurations continued at end of data sheet.
________________________________________________________________ Maxim Integrated Products 1
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim's website at www.maxim-ic.com.
HPDO1
SDA2
SDA1
GND SEL HPIRO HPD VL
HDMI 2:1 Low-Frequency Translating Switch MAX4929E
ABSOLUTE MAXIMUM RATINGS
(All voltages referenced to GND, unless otherwise noted.) V+ ............................................................................-0.3V to +6V All Pins (except GND) .............................................-0.3V to +6V Continuous Current into Any I/O Terminal .........................25mA Continuous Power Dissipation (TA = +70C) 20-Pin QSOP (derate 9.1mW/C above +70C) ..........727mW 20-Pin TQFN (derate 16.9mW/C above +70C) ......1356mW Operating Temperature Range ...........................-40C to +85C Storage Temperature Range .............................-65C to +150C Junction Temperature ......................................................+150C Lead Temperature (soldering, 10s) .................................+300C
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(V+ = +5V 10%, CLP = VL = +3.3V 10%, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25C.)
PARAMETER POWER SUPPLY V+ Supply Current V+ Supply Current VL Supply Current CLP Supply Current ANALOG SWITCH On-Resistance On-Resistance Match Between Channels On-Resistance Flatness Off-Leakage Current On-Leakage Current Output Clamped Voltage RON(SCL_), RON(SDA_) RON RFLAT ISCL_(OFF), ISDA_(OFF) ISCL_(ON), ISDA_(ON) V+ = 4.5V, CLP = 3V, VSCL_ or VSDA_ = 0 to 1.5V; ISCL_ or ISDA_ = 10mA V+ = 4.5V, CLP = 3V, VSCL_ or VSDA_ = 0 to 1.5V; ISCL_ or ISDA_ = 10mA V+ = 4.5V, CLP = 3V, VSCL_ or VSDA_ = 0 to 1.5V; ISCL_ or ISDA_ = 10mA V+ = 5.5V, VSCL_ or VSDA_ = 0V, 5.5V; HIZ1 = HIZ2 = 0V or VL (Note 1) V+ = 5.5V, VSCL_ or VSDA_ = 0V, 5.5V (Note 1) -5 -5 3.3 10 2 25 8 13 +5 +5 A A V I+ I+ IVL ICLP V+ = 5.5V, VL = CLP = 3.6V V+ = 0V, VL = CLP = 0V, VHPIR_ = +5.5V V+ = 5.5V, VL = CLP = 3.6V V+ = 5.5V, VL = CLP = 3.6V 3 8 200 1 1 A A A A SYMBOL CONDITIONS MIN TYP MAX UNITS
VOVC(SCLO), V+ = 5V, CLP = 3.3V, VL = 5V, RP = 1k VOVC(SDAO) (Note 2) CSCL_(OFF), V+ = 5V, TA = +25C, Figure 1 CSDA_(OFF) CSCL_(ON), CSDA_(ON) BW VCT VISO VIL VIH IINL V+ = 5V, TA = +25C, Figure 1 RS = RL = 50, CL = 10pF RS = RL = 50, f = 1MHz, Figure 2 (Note 3) RS = RL = 50, f = 1MHz, Figure 2 (Note 4) V+ = 4.5V V+ = 5.5V 3.8
SWITCH DYNAMIC CHARACTERISTICS SCL_, SDA_ Off-Capacitance SCL_, SDA_ On-Capacitance Bandwidth Crosstalk Off-Isolation LOGIC INPUT (HPIR1, HPIR2) Input Logic-Low Voltage Input Logic-High Voltage Input Logic Leakage 0.8 0.01 1 V V A 20 30 40 -75 -70 pF pF MHz dB dB
2
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HDMI 2:1 Low-Frequency Translating Switch
ELECTRICAL CHARACTERISTICS (continued)
(V+ = +5V 10%, CLP = VL = +3.3V 10%, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25C.)
PARAMETER Input Logic-Low Voltage Input Logic-High Voltage Hysteresis Input Logic-Leakage Current HPDO_ Output Logic-Low Voltage HPDO_ Output Logic-High Voltage HPIRO Output Logic-Low Voltage HPIRO Output Logic-High Voltage Output-Logic Leakage Current TIMING CHARACTERISTICS tPD(HPDO_) Logic Delay tPD(HPIRO) ESD PROTECTION ESD Protection, Human Body Model EXESD Leakage Current HPIR1, HPIR2, HPDO1, HPDO2, SCL1, SCL2, SDA1, SDA2 (Note 5) HPIRO, HPD, SEL, SCLO, SDAO, HIZ1, HIZ2 (Note 6) 6 kV 2 1.0 A V+ = 4.5V, VL = CLP = 3.0V, CL = 15pF, (SEL = 0V or VL (Figure 3) 33 V+ = 4.5V, VL = CLP = 3.0V, CL = 15pF, SEL = 0V or VL (Figure 3) 33 ns SYMBOL VIL VIH VHYST IINL VOL(HPDO_) V+ = 4.5V, VL = CLP = 3.0V, ISINK = 4mA VOH(HPDO_) V+ = 4.5V, VL = CLP = 3.0V, ISOURCE = 4mA VOL(HPIRO) IO V+ = 4.5V, VL = CLP = 3.0V, ISINK = 2mA 2.5 1 HIZ1 = HIZ2 = 0V or VL VOH(HPIRO) V+ = 4.5V, VL = CLP = 3.0V, ISOURCE = 2mA 4.0 0.5 CONDITIONS V+ = 4.5V, VL = CLP = 3V V+ = 5.5V, VL = CLP = 3.6V 3V VL = CLP 3.6V 2.0 150 0.01 1 0.5 MIN TYP MAX 0.8 UNITS V V mV A V V V V A LOGIC INPUT (SEL, HPD, HIZ1, HIZ2)
MAX4929E
LOGIC OUTPUT (HPDO1, HPDO2, HPIRO)
Note 1: Leakage measured at SCLO or SDAO with SCL_ and SDA_ open. Note 2: Pullup resistor of RP = 1k at SCLO and SDAO. These resistors are necessary for the clamp/translation to operate correctly. Note 3: Crosstalk is measured between any two analog inputs, crosstalk = 20log(VOUT / VIN). Note 4: Off-isolation = 20log10 (VSCLO / VSCL_), VSCLO = output, VSCL_ = input to off switch. Note 5: Referenced to GND. Note 6: Any combination of pin to any other pin.
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3
HDMI 2:1 Low-Frequency Translating Switch MAX4929E
Test Circuits/Timing Diagrams
0.1F +5V +3.3V V+ SDAO/SCLO MAX4929E VL 0.1F CLP SEL CAPACITANCE METER f = 1MHz SDA_/ SCL_ GND HIZ1 HIZ2 VIL OR VIH VL
Figure 1. Channel Off-/On-Capacitance
0.1F
+3.3V +5V 0.1F NETWORK ANALYZER
V OFF-ISOLATION = 20log OUT VIN 50 V ON-LOSS = 20log OUT VIN V CROSSTALK = 20log OUT VIN
0V OR VL
SEL
CLP VL V+ SDAO/ SCLO MAX4929E
VIN
50
SDA1/ SCL1 50
VL
HIZ1 HIZ2
SDA2/ SCL2* GND
VOUT
MEAS
REF
50
50
MEASUREMENTS ARE STANDARDIZED AGAINST SHORTS AT IC TERMINALS. OFF-ISOLATION IS MEASURED BETWEEN SDAO/SCLO AND "OFF" SDA_/SCL_ TERMINAL ON EACH SWITCH. ON-LOSS IS MEASURED BETWEEN SDAO/SCLO AND "ON" SDA_/SCL_ TERMINAL ON EACH SWITCH. CROSSTALK IS MEASURED FROM ONE CHANNEL TO THE OTHER CHANNEL. SIGNAL DIRECTION THROUGH SWITCH IS REVERSED; WORST VALUES ARE RECORDED.
*FOR CROSSTALK THIS PIN IS SCL2. SCL1 AND SCL0 ARE OPEN.
Figure 2. On-Loss, Off-Isolation, and Crosstalk
V+ or VL HPD HPIR_ 0V 50%
t r < 5ns t f < 5ns
VOUT HPDO_ HPIRO 0V
0.9 x V0UT
t PD(HPDO ) t PD(HPIR O)
Figure 3. Logic Delay Timing
4 _______________________________________________________________________________________
HDMI 2:1 Low-Frequency Translating Switch
Typical Operating Characteristics
(V+ = 5V, VL = 3.3V, CLP = 3.3V, TA = +25C, unless otherwise noted.)
ON-RESISTANCE vs. VSCLO
MAX4929E toc01
MAX4929E
ON-RESISTANCE vs. TEMPERATURE
V+ = 4V
MAX4929E toc02
12 10 V+ = 4V ON-RESISTANCE () 8 6 V+ = 4.5V 4 2 0 0 0.5 VSCLO (V) 1.0 V+ = 5V
14 12 ON-RESISTANCE () 10 8 6 4 2 0 V+ = 4.5V
V+ = 5V
1.5
-40
-15
10 35 TEMPERATURE (C)
60
85
SUPPLY CURRENT vs. TEMPERATURE
MAX4929E toc03
ON-LEAKAGE CURRENT vs. TEMPERATURE
V+ = 5.5V VL = CLP = 3.3V
MAX4929E toc04
1.0
40
ON-LEAKAGE CURRENT (nA)
0.8 SUPPLY CURRENT (A)
30
0.6
20
0.4
10
0.2 0 -40 -15 10 35 TEMPERATURE (C) 60 85 -40 -15 10 35 TEMPERATURE (C) 60 85
0
OFF-LEAKAGE CURRENT vs. TEMPERATURE
MAX4929E toc05
FREQUENCY RESPONSE
0 -20 ON-LOSS ON-LOSS (dB) -40 -60 -80 CROSSTALK -100 -120 OFF-ISOLATION
MAX4929E toc06
40 V+ = 5.5V VL = CLP = 3.3V OFF-LEAKAGE CURRENT (nA) 30
20
20
10
0 -40 -15 10 35 TEMPERATURE (C) 60 85
-140 0.1 1 10 FREQUENCY (MHz) 100
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5
HDMI 2:1 Low-Frequency Translating Switch MAX4929E
Pin Description
PIN QSOP 1 2 3 4 5 6 7 8 9 10 TQFN 19 20 1 2 3 4 5 6 7 8 NAME HPDO2 HPIR2 SDA2 SCL2 HPDO1 HPIR1 SDA1 SCL1 V+ CLP FUNCTION Hot-Plug Detect Output 2. Translate logic level of HPD to V+ compatible (See Table 2). Hot-Plug Interrupt Request 2 Serial Data Input. SDA Mux Input 2. Serial Clock Input. SCL Mux Input 2. Hot-Plug Detect Output 1. Translate logic level of HPD to V+ compatible (See Table 2). Hot-Plug Interrupt Request 1 Serial Data Input. SDA Mux Input 1. Serial Clock Input. SCL Mux Input 1. Positive Supply Voltage. Bypass V+ to GND with a 0.1F or greater ceramic capacitor. Clamp-Voltage Reference. Clamp the maximum voltage of SCLO and SDAO. Bypass CLP to GND with a 0.1F or greater ceramic capacitor (See Figure 6 and the Typical Operating Circuit). Logic Supply for HIZ_, SEL, HPD, HPIRO. Bypass VL to GND with a 0.1F or greater ceramic capacitor. VL should have the same voltage level as any MCU interface. Select Input. Logic input for Mux connection (See Table 1). SCL Mux Output. Connect SCLO to EDID EPROM. SDA Mux Output. Connect SDAO to EDID EPROM. Hot-Plug Interrupt Request Output. Translate logic level of HPIR_ to VL compatible (See Table 3). Hot-Plug Detect Input. Logic level on HPD is compatible with MCU. Enable Input 2 (See Table 4). Enable Input 1 (See Table 4). Ground External ESD Discharge. Connect 0.1F capacitor from EXESD to GND. Exposed Paddle. Connect EP to GND or leave EP unconnected.
11 12 13 14 15 16 17 18 19 20 --
9 10 11 12 13 14 15 16 17 18 EP
VL SEL SCLO SDAO HPIRO HPD HIZ2 HIZ1 GND EXESD EP
6
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HDMI 2:1 Low-Frequency Translating Switch
Functional Diagram
MAX4929E
MAX4929E
SDA1 SDAO SDA2
SCL1 SCLO SCL2
HPIR1 HPIR2 HPDO1 HPDO2
HPD LOGIC (V+)
HPD LOGIC (VL)
SEL HPD HPIRO HIZ1 HIZ2 EXESD
V+
GND
CLP
VL
Detailed Description
The MAX4929E low-frequency 2:1 switch is ideal for the low-frequency portion of HDMI/DVI switching applications. The device features three independent voltage inputs that allow the user to match any voltage level encountered in switching without additional components. The V+ range is from 4.5V to 5.5V to match the HDMI/DVI 5V requirements. CLP is set to match the EDID EPROM from 3.3V to 5.5V. VL is connected to the same supply as the system MCU. All pins going to the HDMI/DVI connectors are ESD-protected to 6kV Human Body Model (HBM). The MAX4929E has two enable inputs. The enable function allows the device to operate in normal mode or go into a high-Z state. It is possible to control two MAX4929Es with a single control bit, creating a 4:1 equivalent switch using a minimum of external components (see Figure 6). Supply or signals sequencing are not required for the MAX4929E. Supply voltages V+, VL, and CLP can be
applied in any order. Signals can be applied in any order as well.
Analog Switch
The MAX4929E features a voltage clamp function for the two 2:1 switch. Inputs to SCL_/SDA_ are V+ level compatible. Maximum output voltages of SCLO/SDAO are clamped to CLP. For optimum performance connect the EDID EPROM supply voltage to CLP (see Figure 6). For proper operation of the voltage clamp, connect SCLO/SDAO to CLP through the pullup resistors. For maximum output range, connect CLP to V+. The output of the switch is connected to the EDID EPROM, voltages from 3V to 5.5V are expected.
Logic Inputs
VL is the supply to input logic HIZ_, SEL, and HPD. Connect VL to the same supply as the system MCU for compatibility. V+ is the supply to the input logic of the HPIR1 and HPIR2 inputs.
7
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HDMI 2:1 Low-Frequency Translating Switch MAX4929E
Table 1. Inputs Selection for 2:1 Mux Truth Table
INPUTS SEL 0 0 1 1 X X HIZ1 0 1 0 1 0 1 HIZ2 1 0 1 0 0 1 SWITCH CONNECTIONS SDAO to SDA1, SCLO to SCL1 SDAO to SDA1, SCLO to SCL1 SDAO to SDA2, SCLO to SCL2 SDAO to SDA2, SCLO to SCL2 High Impedance High Impedance
RC 1M CHARGE-CURRENTLIMIT RESISTOR HIGHVOLTAGE DC SOURCE RD 1500 DISCHARGE RESISTANCE DEVICE UNDER TEST
Table 4. Mode of Operation
INPUTS HIZ1 0 0 1 1 HIZ2 0 1 0 1 OUTPUTS MODE OF OPERATION High-Impedance: SDAO, SDA1, SDA2, SCLO, SCL1, SCL2, HPDO1, HPDO2, HPIRO Normal Operation Normal Operation High-Impedance: SDAO, SDA1, SDA2, SCLO, SCL1, SCL2, HPDO1, HPDO2, HPIRO
Table 2. HPD Output Channel Selection
INPUTS SEL X 0 1 X X HPD 0 1 1 X X HIZ1 0 1 0 1 0 1 1 0 HIZ2 1 0 1 0 1 0 1 0 OUTPUTS HPDO1 0 1 0 High Impedance High Impedance HPDO2 0 0 1 High Impedance High Impedance
Cs 100pF
STORAGE CAPACITOR
Figure 4. Human Body ESD Test Model
Logic Outputs
The HPDO_ signals are 5V TTL-compatible, per HDMI/ DVI specifications. HPIRO is VL compatible.
Table 3. HPIRO Output Channel Selection
INPUTS SEL X X 0 0 1 1 X X HPIR1 0 1 0 1 X X X X HPIR2 0 1 X X 0 1 X X HIZ1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 HIZ2 1 0 1 0 1 0 1 0 1 0 1 0 0 1 OUTPUT HPIRO 0 1 0 1 0 1 High Impedance High Impedance
ESD Protection
As with all Maxim devices, ESD-protection structures are incorporated on all pins to protect against ESD encountered during handling and assembly. Additionally, the MAX4929E is protected to 6kV (HBM) on SCL1, SCL2, SDA1, SDA2, HPDO1, HPDO2, HPIR1, and HPIR2 by the HBM.
Human Body Model Several ESD testing standards exist for measuring the robustness against ESD events. The ESD protection of the MAX4929E is characterized with the HBM method. Figure 4 shows the model used to simulate an ESD event resulting from contact with the human body. The model consists of a 100pF storage capacitor that is charged to a high voltage, then discharged through a 1.5k resistor. Figure 5 shows the current waveform when the storage capacitor is discharged into a lower impedance. ESD Test Conditions ESD performance depends on a variety of conditions. Contact Maxim for a reliability report documenting test setup, methodology, and results.
8
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HDMI 2:1 Low-Frequency Translating Switch
V+, VL, and CLP to GND using 0.1F or larger ceramic capacitors as close to the device as possible.
MAX4929E
IP 100% 90% AMPERES 36.8% 10% 0 0 tRL TIME
Ir
PEAK-TO-PEAK RINGING (NOT DRAWN TO SCALE)
Hot Plug
The MAX4929E is designed for HDMI/DVI switching. The MAX4929E permits hot-plugging to any inputs/ outputs regardless of the power status of the device. A plug can be inserted, and thus connected to the MAX4929E whether the device is powered up or not. Therefore, sequencing of power supplies is not required; V+, CLP, and VL can be applied in any order.
tDL CURRENT WAVEFORM
Configure Two Devices to Form 4:1 Switch
Two MAX4929Es can be connected together to form a 4:1 switch (see Figure 6).
Figure 5. HBM Discharge Current Waveform
Applications Information
Power-Supply Bypassing and Sequencing
There is no power-supply sequencing required. Power can be applied to V+, CLP, or VL in any order. Bypass
Exposed Paddle
The MAX4929EETP+ provides an EP to improve thermal performance in the TQFN package. Connect the EP to GND or leave EP unconnected.
HDMI1
HPIR1, HPDO1, SCL1, SDA1
MAX4929E
CLP
+3.3V TO +5V +2V TO +3.3V RP 2k RP 2k
HDMI2
HPIR2, HPDO2, SCL2, SDA2 VMCU
EXESD 0.1F EDID EPROM MCU
+5V V+ VL HIZ1 HIZ2 GND
SCLO SDAO HPIRO HPD SEL
CHIP SELECT
HDMI3
HPIR1, HPDO1, SCL1, SDA1
MAX4929E
EXESD 0.1F
HDMI4
HPIR2, HPDO2, SCL2, SDA2 CLP +5V VMCU V+ VL HIZ1 HIZ2 GND SCLO SDAO HPIRO HPD SEL
Figure 6. Two MAX4929Es Connected to Form a 4:1 Translating Switch
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HDMI 2:1 Low-Frequency Translating Switch MAX4929E
Pin Configurations (continued)
PROCESS: BiCMOS
TOP VIEW
Chip Information
HPDO2 1 HPIR2 2 SDA2 3 SCL2 4 HPDO1 5 HPIR1 6 SDA1 7 SCL1 8 V+ 9 CLP 10
20 EXESD 19 GND 18 HIZ1
MAX4929E
17 HIZ2 16 HPD 15 HPIRO 14 SDAO 13 SCLO 12 SEL 11 VL
QSOP
10
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HDMI 2:1 Low-Frequency Translating Switch
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information go to www.maxim-ic.com/packages.) 24L QFN THIN.EPS ______________________________________________________________________________________ 11
MAX4929E
HDMI 2:1 Low-Frequency Translating Switch MAX4929E
Package Information (continued)
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information go to www.maxim-ic.com/packages.)
12
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HDMI 2:1 Low-Frequency Translating Switch
Package Information (continued)
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information go to www.maxim-ic.com/packages.)
MAX4929E
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 13
(c) 2007 Maxim Integrated Products is a registered trademark of Maxim Integrated Products, Inc.
QSOP.EPS

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